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Lattice Semiconductor
Table 3. Register Map for 1GbE PCS Core (Continued)
1GbE PCS IP Core User’s Guide
Address: 0x5
Name: Auto-negotiation Link Partner Ability Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LP_ADV_ABILITY
Default value: 0x0000
Description:
LP_ADV_ABILITY
Address: 0x6
Mode: Read Only
This register contains the Advertised Ability of the Link Partner’s PHY.
Name: Auto-negotiation Expansion Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default value: 0x0000
RESERVED
Mode: Read Only
NP
AN
R
Description:
RESERVED, R
NP
AN
Address: 0xF
Reserved bits are set to zero
Next Page Able (In this core the value is “0”)
New Page Received
Name: Extended Status Register
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FD
Default value: 0x8000
Description:
RESERVED
FD
RESERVED
Mode: Read Only
Reserved bits are set to zero
1000BaseX Full Duplex supported (set to “1” in this core)
7
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